MediaTek CPU team is seeking motivated professionals interested in RTL development for mixed-signal design to join our team as a Senior Digital Design Engineer.
In this role, you will collaborate closely with both the architecture modeling team and the analog design team to:
1. Develop digital designs using SystemVerilog RTL based on system architecture specifications.
2. Collaborate with the design verification team to compile functionality verification plans.
3. Provide design integration guidelines and work with upper-level integrators to resolve related integration issues.
4. Conduct front-end design quality signoff checks
5. Develop design verification testing specifications for the post-Si software team.
You will gain the opportunity to develop state-of-the-art power and performance management used in High-Performance Compute (HPC) products, including the design of clock delivery networks (CDN) and power delivery networks (PDN) for modern CPU/GPU/NPU.
Work Location: Austin, TX, or San Diego, CA
Job Responsibilities
Requirements
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